This application claims priority from Korean Patent Application No. 2002-43698, filed on Jul. 24, 2002, in the Korean Intellectual Property Office, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to methods for fabricating semiconductor devices, and more particularly, to methods for forming a well of a highly-integrated semiconductor devices.
2. Description of the Related Art
A well of a semiconductor device is used to transfer body voltage to a Metal oxide semiconductor (MOS) device that actually operates and eliminate carriers formed because of impact ionization. In order to allow a well to perform these functions, low resistance should be maintained by implanting a large amount of impurities during a well ion implantation process. In particular, low well resistance plays an important role in testing reliability for such problems as latch-up. Thus, a deep well is formed using high-energy ion implantation so as to maintain low resistance. However, high-energy ion implantation causes a decrease in a margin between adjacent wells.
On the other hand, as semiconductor devices become highly integrated, the length of a gate and the width of an active region have been scaled down horizontally. However, the well structure is scaled down in the vertical direction relatively less than in the horizontal direction. This causes a severe deficiency in the margin between adjacent wells, and thus limits the further reduction of chip sizes.
When a well is formed to be shallow using conventional high-energy ion implantation, an increase in resistance causes a malfunction, such as a latch-up, during a device driving operation. In addition, it is well known that the depth of a well in a cell array region bears a close relationship to a soft error rate (SER).